Peripheral Component Interconnect (PCI) Express is an Input/Output system that implements a serial, switched-packet, point-to-point communication standard at the system level. PCI Express has achieved many advantages over the prior shared parallel bus systems, such as quality of service (QoS), high speed peer-to-peer communication between external devices, adaptability, and low pin counts. The basic PCI Express architecture includes a root complex, a PCI Express switch chip, and various external devices. So far, PCI Express switching has only been implemented in a limited number of external devices.
One three-port PCI Express serial switch performs simultaneous comparisons of the target address value of an incoming data packet with the addresses of all possible directly-connected external devices. Since each external device's addressing is defined by a base address and a limit address, there are six comparisons performed for each port. Communication packets can arrive at any of the three ports, so as many as 18 comparisons can be required to be performed, in parallel, within the PCI Express switch, requiring the implementation of sufficient comparators to accomplish the simultaneous comparisons.
As a result of the need to couple more devices to PCI Express systems, there is a need for switches that can accommodate a higher number of external devices. Thus, for example, for a PCI Express switch to accommodate 16 external devices, it would require 16 downstream ports and an upstream port. For a PCI Express switch to have 16 ports or more, the total number of comparisons that would be needed for each packet routing using conventional switch architecture can be as many as 512, or more. Switches having 512 comparators are undesirable since comparators take up chip space, consume power, and increase latency of the system.
Thus, there is a need for a method and apparatus that will accommodate rapid address searching in support of connection of a large number of external devices to a serial switch without using an exponentially increased number of comparators and registers and without incurring undue latency.